In order to reduce pin count, size of packaging, and cost of integrated circuits, it is advantageous to provide data between integrated circuits using a serial interface. However, serial interfaces usually require that both address and data binary values be provided in a time sequential manner which consumes a significant amount of performance within the integrated circuits. Therefore, steps have been taken to eliminate the need for address bits in a serial peripheral interface so that a larger portion of the serial communication time period is spent communicating data rather than overhead.
One prior art technique for avoiding address bits in a serial peripheral interface (SPI) is taught by U.S. Pat. No. 5,146,577, by Babin. In this patent, data is provided by a serial data input port. This serial data provided by the serial data input port is serially shifted into a data serial shift register. While the data is being shifted into the data serial shift register, the number of clocks required to shift in the entire serial data into the data serial shift register is counted via a ripple counter. The final count value of the ripple counter can be used to determine which register is to receive the serially shifted data if all the registers within the system are of different sizes. For example, if the ripple counter contains the value of 8 at the end of a data shift sequence, and only one 8 bit register is located within the system, then it can be easily determined that the data provided in the serial shift register should be provided to the 8 bit internal register. If the ripple counter detects 16 bits and only one register in the system is 16 bits wide, then the data can be accurately routed whereby data bit counting replaces the need for address bits. Since each register has a unique number of data bits of capacity, counting the data bits determines the register which should be written to without the need for additional serially-communicated address bits.
However, when a system becomes more complex and, for example, contains two 8 bit registers (or any two registers of any same size) this clock counting methodology becomes problematic. If two or more registers or two or more sets of registers have the same size, then even if the number of data bits shifted into the system is known it is still unclear as to which of the multiple same-sized registers should receive the data. For example, when there are four 8 bit registers which require communication with the serial data input, the fact that the ripple counter produces the count of 8 is not an adequate indication to determine which of the four 8 bit registers is to receive the data.
In addition, the use of serial address communication prior to, within, or after serial data communication is disadvantageous. Many serial communication interfaces (SCIs) and serial peripheral interfaces (SPIs) require that bits be provided to the serial input in fixed quantities or packets of bits. For example, an interface may require that 8-bit segments be serially provided a whole units to the data input in order to function. This presents no problem as long as 8-bits are required to address 2.sup.8 registers. However, if only two registers are within the system thereby requiring only one bit of addressing, 8 bits must still be provided for addressing thereby wasting 7-out-of-8 bits on an interface that is already slow when compared to the parallel high-frequency operation of most data processors. Therefore, the avoidance of serial address decoding on data lines which require set packets or set number of bits per communication will improve performance.
Therefore, since more registers are being integrated into a single integrated circuit wherein these registers are a same size and require joint access to a serial data interface, a new method for determining which register is to receive serial shifted data needs to be developed. This new method needs to function without additional address pins and avoid the need for a serially provided address value on the data terminal due to serial peripheral interface (SPI) constraints and the desire for improved performance.